Statistics Operations On Two Dimensional Image Processor

ABSTRACT

A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence that includes: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing mathematical operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence that includes: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined at least in part from the mathematical operations of the first sequence. The second sequence further includes performing mathematical operations on items of content from the set of first locations and respective items of content from the set of second locations with the execution lane array.

FIELD OF INVENTION

The description pertains generally to image processing, and, morespecifically, to statistics operations on a two dimensional imageprocessor.

BACKGROUND

Image processing typically involves the processing of pixel values thatare organized into an array. Here, a spatially organized two dimensionalarray captures the two dimensional nature of images (additionaldimensions may include time (e.g., a sequence of two dimensional images)and data type (e.g., colors)). In a typical scenario, the arrayed pixelvalues are provided by a camera that has generated a still image or asequence of frames to capture images of motion. Traditional imageprocessors typically fall on either side of two extremes.

A first extreme performs image processing tasks as software programsexecuting on a general purpose processor or general purpose-likeprocessor (e.g., a general purpose processor with vector instructionenhancements). Although the first extreme typically provides a highlyversatile application software development platform, its use of finergrained data structures combined with the associated overhead (e.g.,instruction fetch and decode, handling of on-chip and off-chip data,speculative execution) ultimately results in larger amounts of energybeing consumed per unit of data during execution of the program code.

A second, opposite extreme applies fixed function hardwired circuitry tomuch larger blocks of data. The use of larger (as opposed to finergrained) blocks of data applied directly to custom designed circuitsgreatly reduces power consumption per unit of data. However, the use ofcustom designed fixed function circuitry generally results in a limitedset of tasks that the processor is able to perform. As such, the widelyversatile programming environment (that is associated with the firstextreme) is lacking in the second extreme.

A technology platform that provides for both highly versatileapplication software development opportunities combined with improvedpower efficiency per unit of data remains a desirable yet missingsolution.

SUMMARY

A method is described that includes loading an array of content into atwo-dimensional shift register. The two-dimensional shift register iscoupled to an execution lane array. The method includes repeatedlyperforming a first sequence that includes: shifting with the shiftregister first content residing along a particular row or column intoanother parallel row or column where second content resides andperforming mathematical operations with a particular corresponding rowor column of the execution lane array on the first and second content.The method also includes repeatedly performing a second sequence thatincludes: shifting with the shift register content from a set of firstlocations along a resultant row or column that is parallel with the rowsor columns of the first sequence into a corresponding set of secondlocations along the resultant row or column. The resultant row or columnhas values determined at least in part from the mathematical operationsof the first sequence. The second sequence further includes performingmathematical operations on items of content from the set of firstlocations and respective items of content from the set of secondlocations with the execution lane array.

An apparatus is described having means for performing the first sequenceabove and for performing the second sequence above.

LIST OF FIGURES

The following description and accompanying drawings are used toillustrate various embodiments. In the drawings:

FIG. 1 shows an embodiment of an image processor hardware architecture;

FIGS. 2a, 2b, 2c, 2d and 2e depict the parsing of image data into a linegroup, the parsing of a line group into a sheet and the operationperformed on a sheet with overlapping stencils;

FIG. 3 shows an embodiment of a stencil processor;

FIG. 4 shows an embodiment of a data computation unit within a stencilprocessor;

FIGS. 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j and 5k depict an example ofthe use of a two-dimensional shift array and an execution lane array todetermine a pair of neighboring output pixel values with overlappingstencils;

FIG. 6 shows an embodiment of a unit cell for an integrated executionlane array and two-dimensional shift array;

FIG. 7 depicts tiles within an image frame;

FIG. 8 depicts raster processing across tile boundaries;

FIG. 9 depicts processing across sheet boundaries;

FIG. 10 depicts processing across sheet and tile boundaries withassociated context switching;

FIG. 11 shows accumulated values within a two dimensional shift registerarray;

FIGS. 12a through 12e depict a reduction process;

FIG. 12f shows window statistics tracking;

FIG. 13 shows random access memories of a stencil processor beingallocated to groups of execution lanes;

FIG. 14 shows a histogram;

FIG. 15a shows a per execution lane allocation of memory space;

FIG. 15b shows a merged per executional lane allocation of memory space;

FIG. 16 shows first and second groups of execution lanes being allocatedto first and second merged memory space regions;

FIGS. 17a through 17c show a histogram reduction process;

FIGS. 18a and 18b show a mechanism for expanding the size of ahistogram;

FIG. 19 shows an integrated camera system and processor;

FIG. 20 shows a statistics method performed by a two dimensional shiftregister;

FIG. 21 shows a computing system.

DETAILED DESCRIPTION a. Image Processor Hardware Architecture andOperation

FIG. 1 shows an embodiment of an architecture 100 for an image processorimplemented in hardware. The image processor may be targeted, forexample, by a compiler that converts program code written for a virtualprocessor within a simulated environment into program code that isactually executed by the hardware processor. As observed in FIG. 1, thearchitecture 100 includes a plurality of line buffer units 101_1 through101_M (hereinafter “line buffers”, “line buffer units” or the like)interconnected to a plurality of stencil processor units 102_1 through102_N (hereinafter “stencil processors”, “stencil processor units” orthe like) and corresponding sheet generator units 103_1 through 103_N(hereinafter “sheet generators”, “sheet generator units” or the like)through a network 104 (e.g., a network on chip (NOC) including an onchip switch network, an on chip ring network or other kind of network).In an embodiment, any line buffer unit may connect to any sheetgenerator and corresponding stencil processor through the network 104.

In an embodiment, program code is compiled and loaded onto acorresponding stencil processor 102 to perform the image processingoperations earlier defined by a software developer (program code mayalso be loaded onto the stencil processor's associated sheet generator103, e.g., depending on design and implementation). In at least someinstances an image processing pipeline may be realized by loading afirst kernel program for a first pipeline stage into a first stencilprocessor 102_1, loading a second kernel program for a second pipelinestage into a second stencil processor 102_2, etc. where the first kernelperforms the functions of the first stage of the pipeline, the secondkernel performs the functions of the second stage of the pipeline, etc.and additional control flow methods are installed to pass output imagedata from one stage of the pipeline to the next stage of the pipeline.

In other configurations, the image processor may be realized as aparallel machine having two or more stencil processors 102_1, 102_2operating the same kernel program code. For example, a highly dense andhigh data rate stream of image data may be processed by spreading framesacross multiple stencil processors each of which perform the samefunction.

In yet other configurations, essentially any directed acyclic graph(DAG) of kernels may be loaded onto the hardware processor byconfiguring respective stencil processors with their own respectivekernel of program code and configuring appropriate control flow hooksinto the hardware to direct output images from one kernel to the inputof a next kernel in the DAG design.

As a general flow, frames of image data are received by a macro I/O unit105 and passed to one or more of the line buffer units 101 on a frame byframe basis. A particular line buffer unit parses its frame of imagedata into a smaller region of image data, referred to as a “line group”,and then passes the line group through the network 104 to a particularsheet generator. A complete or “full” singular line group may becomposed, for example, with the data of multiple contiguous completerows or columns of a frame (for brevity the present specification willmainly refer to contiguous rows). The sheet generator further parses theline group of image data into a smaller region of image data, referredto as a “sheet”, and presents the sheet to its corresponding stencilprocessor.

In the case of an image processing pipeline or a DAG flow having asingle input, generally, input frames are directed to the same linebuffer unit 101_1 which parses the image data into line groups anddirects the line groups to the sheet generator 103_1 whose correspondingstencil processor 102_1 is executing the code of the first kernel in thepipeline/DAG. Upon completion of operations by the stencil processor102_1 on the line groups it processes, the sheet generator 103_1 sendsoutput line groups to a “downstream” line buffer unit 101_2 (in some usecases the output line group may be sent_back to the same line bufferunit 101_1 that earlier had sent the input line groups).

One or more “consumer” kernels that represent the next stage/operationin the pipeline/DAG executing on their own respective other sheetgenerator and stencil processor (e.g., sheet generator 103_2 and stencilprocessor 102_2) then receive from the downstream line buffer unit 101_2the image data generated by the first stencil processor 102_1. In thismanner, a “producer” kernel operating on a first stencil processor hasits output data forwarded to a “consumer” kernel operating on a secondstencil processor where the consumer kernel performs the next set oftasks after the producer kernel consistent with the design of theoverall pipeline or DAG.

A stencil processor 102 is designed to simultaneously operate onmultiple overlapping stencils of image data. The multiple overlappingstencils and internal hardware processing capacity of the stencilprocessor effectively determines the size of a sheet. Here, within astencil processor 102, arrays of execution lanes operate in unison tosimultaneously process the image data surface area covered by themultiple overlapping stencils.

As will be described in more detail below, in various embodiments,sheets of image data are loaded into a two-dimensional register arraystructure within the stencil processor units 102. The use of sheets andthe two-dimensional register array structure is believed to effectivelyprovide for power consumption improvements by moving a large amount ofdata into a large amount of register space as, e.g., a single loadoperation with processing tasks performed directly on the dataimmediately thereafter by an execution lane array. Additionally, the useof an execution lane array and corresponding register array provide fordifferent stencil sizes that are easily programmable/configurable.

FIGS. 2a through 2e illustrate at a high level embodiments of both theparsing activity of a line buffer unit 101, the finer grained parsingactivity of a sheet generator unit 103, as well as the stencilprocessing activity of the stencil processor 102 that is coupled to thesheet generator unit 103.

FIG. 2a depicts an embodiment of an input frame of image data 201. FIG.2a also depicts an outline of three overlapping stencils 202 (eachstencil having a dimension of 3 pixels by 3 pixels) that a stencilprocessor is designed to operate over. The output pixel that eachstencil respectively generates output image data for is highlighted insolid black. For brevity, the three overlapping stencils 202 aredepicted as overlapping only in the vertical direction. It is pertinentto recognize that in actuality a stencil processor may be designed tohave overlapping stencils in both the vertical and horizontaldirections.

Because of the vertical overlapping stencils 202 within the stencilprocessor, as observed in FIG. 2a , there exists a wide band of imagedata within the frame that a single stencil processor can operate over.As will be discussed in more detail below, in an embodiment, the stencilprocessors process data within their overlapping stencils in a left toright fashion across the image data (and then repeat for the next set oflines, in top to bottom order). Thus, as the stencil processors continueforward with their operation, the number of solid black output pixelblocks will grow right-wise horizontally. As discussed above, a linebuffer unit 101 is responsible for parsing a line group of input imagedata from an incoming frame that is sufficient for the stencilprocessors to operate over for an extended number of upcoming cycles. Anexemplary depiction of a line group is illustrated as a shaded region203. In an embodiment, the line buffer unit 101 can comprehend differentdynamics for sending/receiving a line group to/from a sheet generator.For example, according to one mode, referred to as “full group”, thecomplete full width lines of image data are passed between a line bufferunit and a sheet generator. According to a second mode, referred to as“virtually tall”, a line group is passed initially with a subset of fullwidth rows. The remaining rows are then passed sequentially in smaller(less than full width) pieces.

With the line group 203 of the input image data having been defined bythe line buffer unit and passed to the sheet generator unit, the sheetgenerator unit further parses the line group into finer sheets that aremore precisely fitted to the hardware limitations of the stencilprocessor. More specifically, as will be described in more detailfurther below, in an embodiment, each stencil processor consists of atwo dimensional shift register array. The two dimensional shift registerarray essentially shifts image data “beneath” an array of executionlanes where the pattern of the shifting causes each execution lane tooperate on data within its own respective stencil (that is, eachexecution lane processes on its own stencil of information to generatean output for that stencil). In an embodiment, sheets are surface areasof input image data that “fill” or are otherwise loaded into the twodimensional shift register array.

As will be described in more detail below, in various embodiments, thereare actually multiple layers of two dimensional register data that canbe shifted on any cycle. For convenience, much of the presentdescription will simply use the term “two-dimensional shift register”and the like to refer to structures that have one or more such layers oftwo-dimensional register data that can be shifted.

Thus, as observed in FIG. 2b , the sheet generator parses an initialsheet 204 from the line group 203 and provides it to the stencilprocessor (here, the sheet of data corresponds to the five by fiveshaded region that is generally identified by reference number 204). Asobserved in FIGS. 2c and 2d , the stencil processor operates on thesheet of input image data by effectively moving the overlapping stencils202 in a left to right fashion over the sheet. As of FIG. 2d , thenumber of pixels for which an output value could be calculated (nine ina darkened 3 by 3 array) from the data within the sheet is exhausted (noother pixel positions can have an output value determined from theinformation within the sheet). For simplicity the border regions of theimage have been ignored.

As observed in FIG. 2e the sheet generator then provides a next sheet205 for the stencil processor to continue operations on. Note that theinitial positions of the stencils as they begin operation on the nextsheet is the next progression to the right from the point of exhaustionon the first sheet (as depicted previously in FIG. 2d ). With the newsheet 205, the stencils will simply continue moving to the right as thestencil processor operates on the new sheet in the same manner as withthe processing of the first sheet.

Note that there is some overlap between the data of the first sheet 204and the data of the second sheet 205 owing to the border regions ofstencils that surround an output pixel location. The overlap could behandled simply by the sheet generator re-transmitting the overlappingdata twice. In alternate implementations, to feed a next sheet to thestencil processor, the sheet generator may proceed to only send new datato the stencil processor and the stencil processor reuses theoverlapping data from the previous sheet.

b. Stencil Processor Design and Operation

FIG. 3 shows an embodiment of a stencil processor unit architecture 300.As observed in FIG. 3, the stencil processor includes a data computationunit 301, a scalar processor 302 and associated memory 303 and an I/Ounit 304. The data computation unit 301 includes an array of executionlanes 305, a two-dimensional shift array structure 306 and separaterespective random access memories 307 associated with specific rows orcolumns of the array.

The I/O unit 304 is responsible for loading “input” sheets of datareceived from the sheet generator into the data computation unit 301 andstoring “output” sheets of data from the stencil processor into thesheet generator. In an embodiment the loading of sheet data into thedata computation unit 301 entails parsing a received sheet intorows/columns of image data and loading the rows/columns of image datainto the two dimensional shift register structure 306 or respectiverandom access memories 307 of the rows/columns of the execution lanearray (described in more detail below). If the sheet is initially loadedinto memories 307, the individual execution lanes within the executionlane array 305 may then load sheet data into the two-dimensional shiftregister structure 306 from the random access memories 307 whenappropriate (e.g., as a load instruction just prior to operation on thesheet's data). Upon completion of the loading of a sheet of data intothe register structure 306 (whether directly from a sheet generator orfrom memories 307), the execution lanes of the execution lane array 305operate on the data and eventually “write back” finished data as a sheetdirectly back to the sheet generator, or, into the random accessmemories 307. If the execution lanes write back to random accessmemories 907, the I/O unit 304 fetches the data from the random accessmemories 307 to form an output sheet which is then forwarded to thesheet generator.

The scalar processor 302 includes a program controller 309 that readsthe instructions of the stencil processor's program code from scalarmemory 303 and issues the instructions to the execution lanes in theexecution lane array 305. In an embodiment, a single same instruction isbroadcast to all execution lanes within the array 305 to effect a singleinstruction multiple data (SIMD)-like behavior from the data computationunit 301. In an embodiment, the instruction format of the instructionsread from scalar memory 303 and issued to the execution lanes of theexecution lane array 305 includes a very-long-instruction-word (VLIW)type format that includes more than one opcode per instruction. In afurther embodiment, the VLIW format includes both an ALU opcode thatdirects a mathematical function performed by each execution lane's ALU(which, as described below, in an embodiment may specify more than onetraditional ALU operation) and a memory opcode (that directs a memoryoperation for a specific execution lane or set of execution lanes).

The term “execution lane” refers to a set of one or more execution unitscapable of executing an instruction (e.g., logic circuitry that canexecute an instruction). An execution lane can, in various embodiments,include more processor-like functionality beyond just execution units,however. For example, besides one or more execution units, an executionlane may also include logic circuitry that decodes a receivedinstruction, or, in the case of more multiple instruction multiple data(MIMD)-like designs, logic circuitry that fetches and decodes aninstruction. With respect to MIMD-like approaches, although acentralized program control approach has largely been described herein,a more distributed approach may be implemented in various alternativeembodiments (e.g., including program code and a program controllerwithin each execution lane of the array 305).

The combination of an execution lane array 305, program controller 309and two dimensional shift register structure 306 provides a widelyadaptable/configurable hardware platform for a broad range ofprogrammable functions. For example, application software developers areable to program kernels having a wide range of different functionalcapability as well as dimension (e.g., stencil size) given that theindividual execution lanes are able to perform a wide variety offunctions and are able to readily access input image data proximate toany output array location.

Apart from acting as a data store for image data being operated on bythe execution lane array 305, the random access memories 307 may alsokeep one or more look-up tables. In various embodiments one or morescalar look-up tables may also be instantiated within the scalar memory303.

A scalar look-up involves passing the same data value from the samelook-up table from the same index to each of the execution lanes withinthe execution lane array 305. In various embodiments, the VLIWinstruction format described above is expanded to also include a scalaropcode that directs a look-up operation performed by the scalarprocessor into a scalar look-up table. The index that is specified foruse with the opcode may be an immediate operand or fetched from someother data storage location. Regardless, in an embodiment, a look upfrom a scalar look-up table within scalar memory essentially involvesbroadcasting the same data value to all execution lanes within theexecution lane array 305 during a the same clock cycle. Additionaldetails concerning use and operation of look-up tables is providedfurther below.

FIG. 4 shows an embodiment of a data computation unit 401. As observedin FIG. 4, the data computation unit 401 includes an array of executionlanes 405 that are logically positioned “above” a two-dimensional shiftregister array structure 406. As discussed above, in variousembodiments, a sheet of image data provided by a sheet generator isloaded into the two-dimensional shift register 406. The execution lanesthen operate on the sheet data from the register structure 406.

The execution lane array 405 and shift register structure 406 are fixedin position relative to one another. However, the data within the shiftregister array 406 shifts in a strategic and coordinated fashion tocause each execution lane in the execution lane array to process adifferent stencil within the data. As such, each execution lanedetermines the output image value for a different pixel in the outputsheet being generated. From the architecture of FIG. 4 it should beclear that overlapping stencils are not only arranged vertically butalso horizontally as the execution lane array 405 includes verticallyadjacent execution lanes as well as horizontally adjacent executionlanes.

Some notable architectural features of the data computation unit 401include the shift register structure 406 having wider dimensions thanthe execution lane array 405. That is, there is a “halo” of registers409 outside the execution lane array 405. Although the halo 409 is shownto exist on two sides of the execution lane array, depending onimplementation, the halo may exist on less (one) or more (three or four)sides of the execution lane array 405. The halo 405 serves to provide“spill-over” space for data that spills outside the bounds of theexecution lane array 405 as the data is shifting “beneath” the executionlanes 405. As a simple case, a 5×5 stencil centered on the right edge ofthe execution lane array 405 will need four halo register locationsfurther to the right when the stencil's leftmost pixels are processed.For ease of drawing, FIG. 4 shows the registers of the right side of thehalo as only having horizontal shift connections and registers of thebottom side of the halo as only having vertical shift connections when,in a nominal embodiment, registers on either side (right, bottom) wouldhave both horizontal and vertical connections.

Additional spill-over room is provided by random access memories 407that are coupled to each row and/or each column in the array, orportions thereof (e.g., a random access memory may be assigned to a“region” of the execution lane array that spans 4 execution lanes rowwise and 2 execution lanes column wise. For simplicity the remainder ofthe application will refer mainly to row and/or column based allocationschemes). Here, if an execution lane's kernel operations require it toprocess pixel values outside of the two-dimensional shift register array406 (which some image processing routines may require) the plane ofimage data is able to further spill-over, e.g., from the halo region 409into random access memory 407. For example, consider a 6×6 stencil wherethe hardware includes a halo region of only four storage elements to theright of an execution lane on the right edge of the execution lanearray. In this case, the data would need to be shifted further to theright off the right edge of the halo 409 to fully process the stencil.Data that is shifted outside the halo region 409 would then spill-overto random access memory 407. Other applications of the random accessmemories 407 and the stencil processor of FIG. 3 are provided furtherbelow.

FIGS. 5a through 5k demonstrate a working example of the manner in whichimage data is shifted within the two dimensional shift register array“beneath” the execution lane array as alluded to above. As observed inFIG. 5a , the data contents of the two dimensional shift array aredepicted in a first array 507 and the execution lane array is depictedby a frame 505. Also, two neighboring execution lanes 510 within theexecution lane array are simplistically depicted. In this simplisticdepiction 510, each execution lane includes a register R1 that canaccept data from the shift register, accept data from an ALU output(e.g., to behave as an accumulator across cycles), or write output datainto an output destination.

Each execution lane also has available, in a local register R2, thecontents “beneath” it in the two dimensional shift array. Thus, R1 is aphysical register of the execution lane while R2 is a physical registerof the two dimensional shift register array. The execution lane includesan ALU that can operate on operands provided by R1 and/or R2. As will bedescribed in more detail further below, in an embodiment the shiftregister is actually implemented with multiple (a “depth” of)storage/register elements per array location but the shifting activityis limited to one plane of storage elements (e.g., only one plane ofstorage elements can shift per cycle). FIGS. 5a through 5k depict one ofthese deeper register locations as being used to store the resultant Xfrom the respective execution lanes. For illustrative ease the deeperresultant register is drawn alongside rather than beneath itscounterpart register R2.

FIGS. 5a through 5k focus on the calculation of two stencils whosecentral position is aligned with the pair of execution lane positions511 depicted within the execution lane array 505. For ease ofillustration, the pair of execution lanes 510 are drawn as horizontalneighbors when in fact, according to the following example, they arevertical neighbors.

As observed initially in FIG. 5a , the execution lanes 511 are centeredon their central stencil locations. FIG. 5b shows the object codeexecuted by both execution lanes 511. As observed in FIG. 5b the programcode of both execution lanes 511 causes the data within the shiftregister array 507 to shift down one position and shift right oneposition. This aligns both execution lanes 511 to the upper left handcorner of their respective stencils. The program code then causes thedata that is located (in R2) in their respective locations to be loadedinto R1.

As observed in FIG. 5c the program code next causes the pair ofexecution lanes 511 to shift the data within the shift register array507 one unit to the left which causes the value to the right of eachexecution lane's respective position to be shifted into each executionlane′ position. The value in R1 (previous value) is then added with thenew value that has shifted into the execution lane's position (in R2).The resultant is written into R1. As observed in FIG. 5d the sameprocess as described above for FIG. 5c is repeated which causes theresultant R1 to now include the value A+B+C in the upper execution laneand F+G+H in the lower execution lane. At this point both executionlanes 511 have processed the upper row of their respective stencils.Note the spill-over into a halo region on the left side of the executionlane array 505 (if one exists on the left hand side) or into randomaccess memory if a halo region does not exist on the left hand side ofthe execution lane array 505.

As observed in FIG. 5e , the program code next causes the data withinthe shift register array to shift one unit up which causes bothexecution lanes 511 to be aligned with the right edge of the middle rowof their respective stencils. Register R1 of both execution lanes 511currently includes the summation of the stencil's top row and the middlerow's rightmost value. FIGS. 5f and 5g demonstrate continued progressmoving leftwise across the middle row of both execution lane's stencils.The accumulative addition continues such that at the end of processingof FIG. 5g both execution lanes 511 include the summation of the valuesof the top row and the middle row of their respective stencils.

FIG. 5h shows another shift to align each execution lane with itscorresponding stencil's lowest row. FIGS. 5i and 5j show continuedshifting to complete processing over the course of both execution lanes'stencils. FIG. 5k shows additional shifting to align each execution lanewith its correct position in the data array and write the resultantthereto.

In the example of FIGS. 5a-5k note that the object code for the shiftoperations may include an instruction format that identifies thedirection and magnitude of the shift expressed in (X, Y) coordinates.For example, the object code for a shift up by one location may beexpressed in object code as SHIFT 0, +1. As another example, a shift tothe right by one location may expressed in object code as SHIFT +1, 0.In various embodiments shifts of larger magnitude may also be specifiedin object code (e.g., SHIFT 0, +2). Here, if the 2D shift registerhardware only supports shifts by one location per cycle, the instructionmay be interpreted by the machine to require multiple cycle execution,or, the 2D shift register hardware may be designed to support shifts bymore than one location per cycle. Embodiments of the later are describedin more detail further below.

FIG. 6a shows another, more detailed depiction of the unit cell for thearray execution lane and shift register structure (registers in the haloregion do not include a corresponding execution lane). The executionlane and the register space that is associated with each location in theexecution lane array are, in an embodiment, implemented by instantiatingthe circuitry observed in FIG. 6a at each node of the execution lanearray. As observed in FIG. 6a , the unit cell includes an execution lane601 coupled to a register file 602 consisting of four registers R2through R5. During any cycle, the execution lane 601 may read from orwrite to any of registers R1 through R5. For instructions requiring twoinput operands the execution lane may retrieve both of operands from anyof R1 through R5.

In an embodiment, the two dimensional shift register structure isimplemented by permitting, during a single cycle, the contents of any of(only) one of registers R2 through R4 to be shifted “out” to one of itsneighbor's register files through output multiplexer 603, and, havingthe contents of any of (only) one of registers R2 through R4 replacedwith content that is shifted “in” from a corresponding one if itsneighbors through input multiplexers 604 such that shifts betweenneighbors are in a same direction (e.g., all execution lanes shift left,all execution lanes shift right, etc.). Although it may be common for asame register to have its contents shifted out and replaced with contentthat is shifted in on a same cycle, the multiplexer arrangement 603, 604permits for different shift source and shift target registers within asame register file during a same cycle.

As depicted in FIG. 6a , note that during a shift sequence an executionlane will shift content out from its register file 602 to each of itsleft, right, top, and bottom neighbors. In conjunction with the sameshift sequence, the execution lane will also shift content into itsregister file from a particular one of its left, right, top, and bottomneighbors. Again, the shift out target and shift in source should beconsistent with a same shift direction for all execution lanes (e.g., ifthe shift out is to the right neighbor, the shift in should be from theleft neighbor).

Although in one embodiment the content of only one register is permittedto be shifted per execution lane per cycle, other embodiments may permitthe content of more than one register to be shifted in/out. For example,the content of two registers may be shifted out/in during a same cycleif a second instance of the multiplexer circuitry 603, 604 observed inFIG. 6a is incorporated into the design of FIG. 6a . Of course, inembodiments where the content of only one register is permitted to beshifted per cycle, shifts from multiple registers may take place betweenmathematical operations by consuming more clock cycles for shiftsbetween mathematical operations (e.g., the contents of two registers maybe shifted between math ops by consuming two shift ops between the mathops).

If less than all the content of an execution lane's register files areshifted out during a shift sequence note that the content of the nonshifted out registers of each execution lane remain in place (do notshift). As such, any non-shifted content that is not replaced withshifted-in content persists local to the execution lane across theshifting cycle. The memory unit (“M”) observed in each execution lane isused to load/store data from/to the random access memory space that isassociated with the execution lane's row and/or column within theexecution lane array. Here, the M unit acts as a standard M unit in thatit is often used to load/store data that cannot be loaded/stored from/tothe execution lane's own register space. In various embodiments, theprimary operation of the M unit is to write data from a local registerinto memory, and, read data from memory and write it into a localregister.

With respect to the ISA opcodes supported by the ALU unit of thehardware execution lane 601, in various embodiments, the mathematicalopcodes supported by the hardware ALU are integrally tied with (e.g.,substantially the same as) the mathematical opcodes supported by avirtual execution lane (e.g., ADD, SUB, MOV, MUL, MAD, ABS, DIV, SHL,SHR, MIN/MAX, SEL, AND, OR, XOR, NOT). As described just above, memoryaccess instructions can be executed by the execution lane 601 tofetch/store data from/to their associated random access memory.Additionally the hardware execution lane 601 supports shift operationinstructions (right, left, up, down) to shift data within thetwo-dimensional shift register structure. As described above, programcontrol instructions are largely executed by the scalar processor of thestencil processor.

c. Statistics Operations Performed on Stencil Processor

FIG. 7 shows an exemplary depiction of an image frame 600. As observedin FIG. 7, the image 700 can be viewed as being broken down into anarray of tiles. The particular exemplary image of FIG. 7 consists of anarray of 16 tiles by 16 tiles. As observed in FIG. 8 each tile can befurther broken down into an array of sheets. The exemplary depiction ofFIG. 8 shows, e.g., the first two tiles 801, 802 along the top row oftiles of the image 700 of FIG. 7. As FIG. 8 shows, each tile can bebroken down into an array of sheets. In the particular example of FIG.8, each tile is composed of a 16×16 array of sheets. Each sheet may becomposed, for example, of a 16×16 array of pixel values.

As described at length above, in various embodiments, a stencilprocessor is designed to process a sheet as its unit of data. Here, asheet of image data is loaded into the stencil processor's twodimensional register space and the processor performs certain imageprocessing tasks on the sheet of image data. As observed in FIG. 8, invarious embodiments, the processing of an entire image includes, e.g.,processing a row of sheets across a first tile 801 (e.g., in a left toright fashion across the tile) and then continuing to process sheets ina same direction along the same row within a second neighboring tile802.

The process continues until all sheets along the particular row areprocessed across all tiles of the image. Then a next (e.g., lower) rowof sheets is processed and the process repeats. For instance after thesixteenth sheet of the sixteenth tile along the first row of sheets ofthe image is processed, the first sheet of the first tile along thesecond row of sheets is next processed.

The processing of statistics for an image often entails calculating asummation of pixel values within the image. For example, a commonstatistics operation is to calculate an average pixel value. As such,pixel values are summed across an image and then normalized by thenumber of pixels that were summed over. In various embodiments, imagestatistics are organized at tile granularity. As such, e.g., an averagepixel value is maintained for each tile in an image. The tiles are thensubsequently processed as needed to calculate other statistics for theimage.

FIG. 9 shows one approach for summing pixel values within a tile. FIG. 9depicts the sheet arrangement for the upper left hand corner of a tile.As observed in FIG. 9, same positioned pixel values within a sheet arrayare summed over multiple sheets. For example, the upper leftmost pixelvalue of Sheet_0 is added with the upper leftmost pixel value ofSheet_1. The resulting summation is then added to the upper leftmostpixel value of Sheet_2. The process continues until all sheets in thetile have been accounted for.

Recalling that the stencil processor processes data in units of sheets,the summation itself is performed on a sheet by sheet basis. Asdescribed above, in an embodiment, a stencil processor includes anexecution lane and associated register space for each array locationwithin a sheet. Initially, Sheet_0 is loaded into the stencilprocessor's two dimensional shift register structure and processed. Apixel value associated with each array location in the sheet is kept inthe local register space of that array location within the twodimensional shift register. Then Sheet_1 is loaded into the stencilprocessor's two dimensional shift register structure and processed.

A pixel value associated with each array location in Sheet_1 is added tothe pixel value for the same array location in Sheet_0. The resultantfor each array location is kept in the local register space of thatlocation in the two-dimensional shift register structure and the processcontinues. Thus, with each new sheet that the stencil processorprocesses, a summation across all sheets processed so far can beaccumulated for all array locations within the sheet. In an alternateapproach, the above process is performed except that the accumulatedsummation data is kept in a stencil processor's internal memory spacerather than register space (e.g., referring to FIG. 3, the RAM 307 thatis coupled to the memory execution units of the executional array 305and/or the scalar memory 303 that is associated with the scalarprocessor 303). In another alternate embodiment, the accumulatedsummation data is kept in memory that is external to the stencilprocessor such as memory that is coupled to a line buffer unit 101.

Comparing FIGS. 8 and 9, note that Sheet_16 of tile 0 will not beprocessed until after Sheet_15 of tile 15 has been processed. That is, asame row of sheets are processed across tiles. Thus, if statistics aretracked on a tile by tile basis, statistics context needs to switch eachtime the processing progresses across tile boundaries. FIG. 10graphically depicts the context switching process. Here, a datastructure that keeps statistics for a particular tile is assumed to becreated and resident in the register space or internal memory space of astencil processor when the stencil processor is processing thatparticular tile.

For instance, while sheets 0 through 15 are being processed for Tile_0,a statistics data structure for Tile_0 is kept in the internal memoryand/or two-dimensional register space of the stencil processor. AfterSheet_15 is processed for Tile_0, at time 1001, the statistics datastructure for Tile_0 is switched out of the stencil processor's twodimensional register space or internal memory space and the statisticsdata structure for Tile_1 is switched into the stencil processor'sregister space or internal memory space. Likewise, at time 1002, inbetween the processing of Sheet_15 of Tile_1 and Sheet_0 of Tile_2, thestatistics data structure for Tile_1 is switched out of the stencilprocessor's register space or internal memory and the statistics datastructure for Tile_2 switched into the stencil processor's register ormemory space.

After Sheet_15 of Tile_15 is processed, at time 1016, the statisticsdata structure of Tile_15 is switched out of the register or internalmemory space of the stencil processor and the statistics data structurefor Tile_0 is switched back into the register or internal memory spaceof the stencil processor as the process begins processing of the secondrow of sheets within the image. Likewise, at time 1001, the statisticsdata structure for Tile_0 is switched out of the stencil processor'sregister space or internal memory space and the statistics datastructure for Tile_1 is switched into the stencil processor's registerspace or internal memory space. Processing then continues in thisfashion until all sheets of tiles 0 through 15 have been processed atwhich point the statistics data structures for each of tiles 0 through15 are complete. The process then continues for the second row of sheetswithin the image.

FIG. 11 shows an exemplary depiction of the aforementioned statisticsdata structure that may be kept for a particular tile. Here, asdiscussed above, for example, the statistics data structure may keep asummation of all pixel values at a same pixel location within a sheet ofthe tile. A “complete” data structure is created for the tile when allsheets within the tile have been summed over. That is, a complete datastructure includes a summation at the same sheet pixel location acrossall sheets within the tile. For illustrative ease, FIG. 11 onlygraphically depicts the summation at the four corner pixel locations ofthe sheet.

An additional statistical process is to reduce the entire accumulatedarray of FIG. 11 into a scalar value that, e.g., sums over all the pixellocations of the array of FIG. 11, which, in turn, corresponds to asummation of all of the pixel values within the entire tile. That is,with FIG. 11 being array of the summation of all pixel values within atile at a same sheet pixel location, the summation across all elementsin the array of FIG. 11 corresponds to the summation of all pixel valueswithin a tile on a sheet pixel location by sheet pixel location basis.FIGS. 12a through 12e show the reduction of the entire array into ascalar. As will be evident from the discussion of FIGS. 12a through 12e, the reduction process makes particular use of the two dimensionalshift register array that is a component of the stencil processor.

Here, the statistics array of FIG. 11 is assumed to be initially loadedinto the two dimensional shift array of the stencil processor. FIG. 12ashows a first shift action of the shift register in which every othercolumn of data is shifted into its left neighbor. Each shift depicted inFIG. 12a includes a pixel value being shifted and a pixel value in thelocation that the shifted pixel value is shifted into. These pair ofpixel values are then added in the execution lane that is shifted intoand kept in the register space of the same execution lane.

As such, after the completion of the shift of FIG. 12a and the followingsummation every other column of the array includes a summation of theneighboring pair of pixel values in the register space of each pixellocation of the column. That is, e.g., column 1201 includes a summationof neighboring pixel values in every pixel location of column 1201,column 1202 includes a summation of neighboring pixel values in everypixel location of column 1202, etc. Note that all the shifts observed inFIG. 12a may occur in a single cycle, and, the summation may occur in animmediately following cycle. As such, the reduction can reduce the arrayby 50% in only two cycles (cycles C1 and C2).

As observed in FIG. 12b , nearest neighbor columns having a summationfrom the operation of FIG. 12a are shifted and added. That is, after theoperation of FIG. 12a , only columns 1200, 1202, 1204, 1206, 1208, 1210,1212, and 1214 have summation content from the summation operation ofFIG. 12a (the other columns may also have summation content but theircontent is not utilized, in an embodiment, the shift and summationsoperations that determine the unused content is not performed to savepower). As such, pixel values of column 1202 are shifted to the left bytwo array locations into column 1200. Corresponding source todestination pairs also exist for columns 1206 to 1204, 1210 to 1208, and1214 to 1212. As with the operation of FIG. 12, the pixel value pairsare added by the execution lane logic at the destination. As such, afterthe operation of FIG. 12b , summation values now exist in columns 1200,1204, 1208, and 1212. Note that in an embodiment, the two dimensionalshift register is able to perform “two location hop” shifts in a singlecycle. Thus, all of the shifts observed n FIG. 12b can be performed in asingle cycle (C3) and the summation operation can be performed in animmediately following cycle (C4). As such, after four cycles, thereduction operation can reduce the array of FIG. 11 by 75%.

Here, however, it is pertinent to point out that in various embodimentseach execution lane has multiple registers. That is, referring brieflyback to FIG. 6, each execution lane has multiple registers R1 through R5for shifting data in/out and/or storing a resultant from an ALUoperation. Additionally, many image processing algorithms have multiple“channels” of data. For example, an image composed of red (R), green(G), and blue (B) pixels may process a first channel composed ofsheets/tiles/frames of R data separately from a second channel composedof sheets/tiles/frames of G data all of which are processed separatelyfrom a third channel of sheets/tiles/frames of B data.

Although the aforementioned example of FIGS. 12a and 12b indicated twocycles must be consumed to perform a shift and a summation, it ispertinent to recognize that this limitation only applies to operationswithin a same channel because of the summation's dependence on a priorshift. Importantly, in an embodiment, the execution lane array receivesa VLIW type instruction word that can specify both a shift operation andan ALU operation within a single cycle. With this instruction format andmultiple registers per array location, two different channels can besimultaneously reduced according to the core process of FIGS. 12a and12b . That is, in a software pipelined loop like fashion, e.g., in afirst cycle R is shifted and G is summed, and, in a second followingcycle the just shifted R is summed and the resultant from the justsummed G is shifted. In this fashion, the overall processor can performa shift and summation reduction in, e.g., every cycle across twochannels.

As observed in FIG. 12c , the reduction process continues but with(again) longer shifts. Here, pixel values of column 1204 are shiftedinto column 1200 and added in column 1200, and, pixel values of column1212 are shifted into column 1208 and added in column 1208. As such,after the operation of FIG. 12c (which again may only consume the nexttwo cycles (C5 and C6) assuming the two dimensional shift registersupports, e.g., shifts of 4 unit locations), summation values only existin columns 1200 and 1208. FIG. 12d shows complete reduction along thehorizontal axis as the values in column 1208 are shifted into column1200 and added within column 1200. Again, assuming the two dimensionalshift register can perform the shift observed in FIG. 12d in a singlecycle, the reduction of FIG. 12d is reached by the eight cycle C8 (in anembodiment, the shift register does not generally support shifts of themagnitude observed in FIG. 12d but does support, in a single cycle, ashift from column 1208 to column 1200).

FIG. 12e shows the subsequent reductions that are performed along column1200 which ultimately reduce the entire array to a scalar summationvalue as of cycle C16. The reductions of FIG. 12e are essentially thesame reductions of FIGS. 12a through 12d but in the vertical directionand only along one column. In an embodiment, as with the horizontalreductions of FIGS. 12a through 12d , each reduction sequence consumesone cycle for the shift register to perform its corresponding shift andanother cycle is consumed adding a local value with a value that wasjust shifted into the same location.

The above discussion of the reduction process of FIGS. 12a through 12ewas directed to an embodiment where, as shown in FIG. 11, a separatesummation value was maintained for each pixel location in a sheet forall sheets within a tile. As discussed with respect to FIG. 10, however,before a “complete” statistics structure for a particular tile can berealized, all rows in the tile need to be processed. Because scanningacross an image row will cross multiple tiles, data structures for thetiles are context switched in and out with each crossing of a tileboundary.

Each per tile statistics data structure therefore includes a summationvalue or “counter” for each pixel location within a sheet for the sheetsthat have so far been processed. Thus, the dimensions of the statisticsdata structure for a tile correspond to the dimensions of a sheet withinthe tile (e.g., 16×16 summation values). If multiple tiles exist withinan image (as suggested by FIGS. 9 and 10), the amount of statistics datathat is kept for an image can be large (i.e., (the number of tiles inthe image)×(the number of counters per tile)). Here, reduction of a tileinto a scalar as soon as a complete data structure exists for a tile canhelp ease the statistics tracking burden.

Alternatively, referring back to FIG. 10, the statistics array can bereduced to a scalar each time it is to be context switched out. Forinstance, the statistics array for tile_0 may be reduced to a scalar attime 1001 just before it is stored and again at time 1017 just before itis stored. Here, performing the reduction of FIGS. 12a through 12ebefore each context switch out may consume more processing (multiplescalar reductions are performed per tile rather than one scalarreduction per tile), but the data footprint size of the statistics beingswitched out is much smaller which makes it more likely the switched outstatistics data can be kept internally within the stencil processormemory rather than being directed across the entire image processor toline buffer memory.

Other statistical processes may be less burdensome. For example,according to one statistics keeping mode referred to as “global”, anentire frame/image is deemed to consume only a single tile. Thereforeonly one statistical data structure exists and context switching doesnot arise (i.e., no tile boundaries are crossed in the raster scanprocessing). The data structure is “complete” when all sheets within theimage have been processed at which point a scalar for the entire imagecan be created by performing the reduction of FIGS. 12a though 12 ediscussed just above.

In another statistics tracking mode, depicted in FIG. 12f , statisticsare kept for one or more “windows” 1251, 1252, 1253 within an image 1250that may or may not overlap in various combinations. Sheets may beprocessed in a particular pattern (e.g., from left to right across theimage before dropping down to process a next row). While processingwithin a particular window statistics are accumulated for each pixellocation with the sheet dimensions consistent with the discussion ofFIG. 9 above. Upon leaving a window the accumulation activity stops. Thestatistical accumulation restarts upon the raster scan eventuallycrossing back into the window.

For example, referring to FIG. 12f , statistics accumulations will stopfor window 1251 as the raster scan follows path 1254 and crosses out ofwindow 1251 but will recommence when the raster scan reaches path 1255and crosses back into window 1251. Note that this behavior is followedfor all windows which can result in statistics being concurrentlyaccumulated for regions of overlapping windows. For example, referringto raster scan path 1256, statistics tracking will restart for window1251 when point A is reached. Some time later statistics tracking willrestart for window 1252 when point B is reached. A further time laterstatistics tracking will cease for window 1251 when point C is reachedand then for window 1252 when point D is reached. Once accumulationshave completed for a window after the raster scan has covered the entiresurface area of a window, the data that was accumulated for the window(again, one accumulated value per pixel location within a sheet) may bereduced according to the process discussed above with respect to FIGS.12a through 12 e.

Recall from the discussion of FIG. 4 that random access memories 407 maybe coupled to the execution lane array 405 and two dimensional shiftregister 406 to give the stencil processor a local system memoryfunction. Here, multiple execution lanes within the execution lane array405 may share a same random access memory unit. For example, referringto FIG. 4, a first subset of execution lanes may be coupled to randomaccess memory 407_1, a second subset of execution lanes may be coupledto random access memory 407_2, etc. FIG. 4 shows one approach whereexecution lanes that reside along a same row are coupled to a samerandom access memory.

FIG. 13 shows another approach where two dimensional blocks of executionlanes are coupled to a same random access memory. In the particularexample of FIG. 13, blocks of four execution lanes are coupled to a samerandom access memory. Here, for instance, the upper leftmost block offour execution lanes are coupled to random access memory 1307_1, theupper rightmost block of four execution lanes are coupled to randomaccess memory 1307_2, etc. Other separate blocks of four execution lanesare presumed to be coupled to their own respective random access memorybut are not depicted for illustrative ease.

Another common set of statistics that are kept for an image are ahistogram. A histogram essentially divides a particular parameter into anumber of bins. For example, an eight bit intensity value can be brokendown into 256 separate bins (one bin for each unique eight bit value).The number of times a value is observed in the data of an image is kepttrack of each bin. As such, e.g., the number of times each unique eightbit value is observed is individually recorded with a count value foreach bin. The spread of respective count values across the set of binscorresponds to a histogram. FIG. 14 shows an exemplary depiction of ahistogram showing a separate count (along the vertical axis) for each ofmultiple bins (along the horizontal axis).

FIGS. 15a and 15b pertain to a technique for extending the capabilitiesof the stencil processor of FIGS. 4 and 13 to generate high resolutionhistograms. That is, a histogram with a large number of bins. FIG. 15ashows an embodiment of a nominal design point of the stencil processorof FIGS. 4 and 13 in which each execution lane within a group ofexecution lanes that share a same random access memory is provided itsown private memory space within the random access memory. Here,referring to FIG. 15a , the set of four execution lanes 1501 are eachcoupled to random access memory 1507. However, each execution lane isnominally design to only access its own private space within randomaccess memory 1507. As drawn in FIG. 15, for example, execution lane1501_1 is designed to only access addressable region 1502_1 withinrandom access memory. Other partitions of random access memory 1507 areobserved being allocated for the other execution lanes within the group1501.

A problem with the per execution lane memory partitioning of FIG. 15a isthat the partitions effectively limit the number of histogram bins thatthe execution lanes can bin observed data to. That is, because eachpartition corresponds to a limited amount of memory space, eachexecution lane can only bin data items across a total number of binsthat can be established within a single partition. This may have theundesirable effect of limiting the resolution of the histograms that theexecution lanes can bin to (note also that in various embodiments onlyone of the execution lanes in a group may access the memory in a givencycle).

As such, FIG. 15b shows a better approach in which, at least during ahistogram mode, the partitions within a random access memory areeffectively merged so that each execution lane that shares the randommemory can freely access the total amount of merged space. Merging thepartitions and permitting each of the execution lanes that share therandom access memory to freely access the total amount of merged spaceeffectively provides for a wider data field that accommodate more bins.With more bins being accommodated for, higher resolution histograms canresult. As such, for example, if a single partition of the approach ofFIG. 15a can only hold count values for 256 bins, the merged space ofFIG. 15b can hold count values for 1024 bins. Thus, the execution lanesof the approach of FIG. 15a can only generate histograms having 256 binswhile the same execution lanes in the approach of FIG. 15b can generatehistograms having 1024 bins. Other embodiments can have other numbers ofbins.

FIGS. 16 and 17 a through 17 c pertain to an approach in which ahistogram can be determined across an entire image by first having theexecution lanes bin observed data to their local memories and then usingthe two-dimensional shift register structure and ALU capabilities of theexecution lanes to tabulate respective counts over the bins.

FIG. 16 shows a high level depiction in which neighboring executionlanes are grouped into neighboring blocks of four where each group isgiven access to a respective random access memory, where, the space ofeach random access memory is merged so that each execution lane within asame group can access the same merged memory space as described justabove with respect to the description of FIGS. 15a and 15b . Forsimplicity only two blocks of groups execution lanes 1601, 1602 aredepicted along with their corresponding respective merged memory space1607_1, 1607_2.

To generate a histogram, a series of sheets for an image are loaded intothe two-dimensional shift register. The bins of the histogram areallocated in the merged memory space for each execution lane group andthe individual execution lanes increment a respective count valuemaintained for each bin within the merged memory space for theparticular value that each execution lane observes. For example, ifexecution lanes 1, 2, 3, and 4 within a same group respectively observevalues corresponding to bins 4, 9, 12, and 21, then, execution lane willupdate the count value for bin 4, execution lane 2 will update the countvalue for bin 9, execution lane 3 will update the count value for bin12, and execution lane 4 will update the count value for bin 21. Invarious embodiments, because only one execution lane can access thememory that a group of execution lanes share, the execution lanes willperform their aforementioned updates in consecutive cycles.

After a number of sheets have been processed for the image, the mergedmemory space of each of the random access memories essentially containsa histogram for its constituent execution lanes. For example, referringto FIG. 16, the merged memory space within random access memory 1607_1contains the histogram data for execution lanes within group 1601 andthe merged memory space within random access memory 1607_2 contains thehistogram data for the execution lanes within group 1602.

A next operation then is to merge the content of each random accessmemory so that a histogram for all execution lanes can be realized. FIG.17a pertains to a simplistic example, in which the histogram onlycontains 32 bins (bins 0 to 31). Here, for each group of execution lanesand their corresponding merged memory space, the count values for bins 0to 7 are loaded into the register space of the upper left executionlane, the count values for bins 8 to 15 are loaded into the registerspace of the upper right execution lane, the count values for bins 16 to23 are loaded into the register space for the lower right executionlane, and the count values for bins 24 to 31 are loaded into theregister space for the lower left execution lane. FIG. 17a shows thecontent of the respective register space of the execution lanes forgroups 1701 and 1702. Again, only two groups are shown for illustrativeease and in various embodiments the content pattern for groups 1701 are1702 are repeated across all groups within the execution lane array. Inembodiments, the loaded register content takes the form of a vector datastructure that maintains respective count value for different bitpositions in the data structure where the different bit positionscorrespond to the different bins being maintained by the data structure.

FIG. 17b shows a first reduction sequence in which the histogram contentof execution lanes from a first group is shifted into the register spaceof same relative positioned execution lanes from a second group. Thatis, e.g., the upper left execution lane of the second group 1702 has itsregister content shifted into the register space of the upper leftexecution lane of the first group 1701 to consolidate the histogram datafor bins 0 through 7 collected across both groups 1701, 1702 into theregister space of the upper left execution lane of group 1701. Acorresponding operation is performed for the other three execution lanepositions. Note that the shift can occur in a single cycle assuming thetwo dimensional shift register can shift data structures of appropriatesize across two array lane locations in a single cycle. If the bincontent for 8 bins consumes more data than can be shifted in a singlecycle, then multiple cycles may be used.

Regardless, after the bin content for the second group 1702 has beenshifted into the register space of the first group 1701, the executionlanes perform a vector add of their respective pairs of bin data toaccumulate total count values for their respective bins. That is, e.g.,after the vector add operation, the upper execution lane of group 1701will contain a data structure that has the total count for each of bins0 through 7 that was tabulated by both groups 1701 and 1702. Acorresponding accumulation of count values will also exist in theregister space of the other three execution lanes of group 1701. Again,like the shift operation, the vector summation can also be performed ina single cycle in various embodiments. Again, although FIGS. 17a and 17bonly show two groups, in various embodiments the operations of FIGS. 17aand 17 are simultaneously performed for all pairs of groups in theexecution lane array.

FIG. 17c shows a next iteration in which the accumulated counts thatwere just tabulated (e.g., as of FIG. 17b ) are again consolidatedaccording to a similar process (except that the shift length is longer).For instance, referring briefly back to FIG. 17b , one can envisionanother pair of groups 1703, 1704 of four execution lanes each thatphysically reside directly beneath group 1702 in the array. FIG. 17cshows both of these groups 1703, 1704. After the operation of FIG. 17bis completed, the content of groups 1703 and 1704 will be accumulated ingroup 1703. As such, the operation of FIG. 17c shifts the accumulatedcontent of group 1703 being shifted into the register space of group1701. After the vector add operation of FIG. 17c , group 1701 willcontain accumulated counts for all bins as originally tabulated by eachof groups 1701 through 1704. In the simplistic 8×8 execution lane arrayof FIG. 17c , all values will have been accumulated into the top row ofgroups after the vector add operations of FIG. 17 c.

From here, a horizontal reduction amongst the top row of groups cancommence similar to the vertical reductions of FIG. 12e (with eachdifferent execution lane location within a group continuing to maintainits own set of bins). Eventually the process will consolidate to asingle group where each array location in the group has the total countacross the image for its corresponding bins.

In various embodiments, histograms are keep track of at tilegranularity. As such, context switching of histogram data similar to thecontext switching discussed above with respect to FIG. 10 can beperformed during accumulation of the histogram. Here, for instance, theaforementioned merged data structures within the processor's randomaccess memories are configured to store histogram data only for aspecific tile. When the raster scanned processing of image data causestile boundaries to be crossed over, the histogram data structure for thetile that processing just departed from is switched out (e.g., by beingwritten out of the stencil processor memories into, e.g., a line buffer)and histogram data structures for the tile that processing just enteredis switched in (e.g., be being written into the stencil processingmemories). After the raster scanning fully processes a complete tile,the reductions of FIGS. 17a through 17c and thereafter can be performedto determine a complete histogram for the entire tile.

Note that, conceivably, lower resolution histograms may not requiremerged storage space in the random access memories of the stencilprocessor. Here, for instance, the dedicated per execution lane memoryspace of FIG. 15a may be sufficient to hold all the bins for a lowerresolution histogram. As such, merging of the per execution lane memoryspaces may not be necessary (and therefore may only be entertained forhigh resolution histograms). Further still, some histograms may be ofsufficiently low resolution that the bin count values may be kept in therespective register space of the execution lanes (here, the registerfile may be dynamically indexed with a pixel value such that eachexecution lane could access a different register). In this case use ofthe random access memories is not necessary. For lower resolutionhistograms, such as those that do not require merging of per executionlane dedicated memory or register space, bin totals may be accumulatedusing the processes of FIGS. 12a through 12e rather than FIGS. 17athrough 17 c.

Similarly, with respect to context switching, it is conceivable thatonly high resolution histogram data structures will need to be switchedout of the stencil processor memory or register space (e.g., into a linebuffer). Here, lower resolution histograms may be able to keep “switchedout” histogram data context in the local memories and/or register spaceof the stencil processor.

FIGS. 16 and 17 a-17 c described a mechanism for a group of executionlanes to collectively share the memory resources that they are coupledto in order to allow for histograms with a larger number of bins. Bycontrast, FIGS. 18a and 18b describe a mechanism by which the bin countof a histogram can be extended across execution lanes of differentgroups. FIG. 18a shows, e.g., the upper left hand corner of theexecution lane array. Here a first 4×2 group 1810 of execution lanes anda second 4×2 group of execution lanes 1811 are observed. Both groups1810, 1811 may share memory resources to expand bin size as describedabove with respect to FIGS. 16 and 17 a-c.

Here, if each of groups 1810, 1811 are able to individually support 1024different histogram bins, both of groups 1810, 1811 could also belogically combined to support 2048 bins. Thus, histogram size in termsof number of bins can be expanded by combining groups of executionlanes. According to one approach referred to as “spatial”, the differentexecution lane groups within a same logical combination are responsiblefor binning into different bin ranges. For example, the execution laneswithin group 1810 are responsible for binning into bins 0 through 1023and the execution lanes within group 1811 are responsible for binninginto bins 1024 through 2047. Thus, in order to fully process input pixeldata so that it is guaranteed to be placed into the particular correctbin that it should be placed into, data is shifted as observed in FIG.18b . That is, e.g., data that is to be binned is first loaded into theexecution lanes of the first group 1810 and if any the data items fallwithin bins 0-1023 they are binned by their respective execution lanesin group 1810. After the initial binning processing, the data that wasloaded into the first group is shifted into the second group 1811 asobserved in FIG. 18b . Any remaining items of data that were not binnedby the first group because they fell with bin ranges 1024-2047 will bebinned by respective execution lanes within group 1811.

Thus, in this example, data is initially loaded into every lane of everygroup in the execution lane array and the entire array performsprocessing on the data with shifts in between binning processes. Forinstance, data is initially loaded into both of groups 1810 and 1811.After the data is loaded, group 1810 bins those data values that wereloaded into group 1810 that fall into bins 0-1023 and group 1811 binsthose data values that were loaded into group 1811 that fall into bins1024-2047. After this initially binning sequence, the data that wasoriginally loaded into group 1810 is shifted into group 1811 and thedata that was originally loaded into group 1811 is shifted into anothergroup (such as the group directly beneath group 1811) that bins intobins 0-1023). For simplicity FIG. 18b does not show the shifting of thedata that was originally loaded into group 1811. Note that bin sizes caneven be further extended by combining more than two groups. Forinstance, the 4×2 group of execution lanes directly beneath group 1811can be used to bin into bin range 2048-3072.

In another alternative binning expansion approach referred to astemporal, rather than combine physical groups of execution lanes and usethe two-dimensional shift register to shift between combined groups,instead, groups of execution lanes are not combined. Rather, the binningranges are context switched in and out of the execution lanes. In thiscase, e.g., data is initially loaded into all execution lane groups.During a first iteration each group bins according to a first bin range(e.g., bins 0-1023). After binning into the first range is complete, thedata is not shifted within the register array, but binning contextinformation that determines which binning ranges apply are switched(e.g., context for binning into ranges 0-1023 are switched out of theexecution lane groups and context for binning into ranges 1024-2047 areswitched into the execution lane groups). The execution lanes thenre-execute a binning process for the new, higher range. The processcontinues until after the final binning range context is switched in anbinned to.

In various embodiments the image processor has configuration registerspace to establish any of the operating modes described above (e.g.,context switching out of the stencil processor, merging of executionlane register space, global statistics tracking, per tile statisticstracking, window statistics tracking, etc.). The statistics operationsdescribed above can be codified in program code (e.g., object codeexecuted by a stencil processor) and stored on a machine readablestorage medium.

Although various embodiments above have applied processes to rows incertain situations and columns in certain other situations, it should bereadily apparent that processes performed on rows can instead beperformed on columns and vice-versa.

FIG. 19 shows an integrated camera 1901, ISP/IPU, and processor 1902.The camera 1901 may include a lens assembly 1907 and image sensor 1906.Raw image data from the camera 1901 may be passed from the camera 1901to an ISP subsystem that includes an image signal processor (ISP) and/orimage processing unit (IPU) 1904 and a camera statistics unit 1905. Invarious embodiments, the camera statistics unit 1905 is a hardwarecomponent that calculates statistics from the raw image data that isgenerated by the camera 1901 with dedicated logic circuitry. In stillyet other embodiments, the camera statistics unit 1905 is a softwarecomponent and camera statistics are executed on IPU hardware 1904 whichis capable of executing program code (here, image signal processing(ISP) hardware is traditionally not capable of executing program code).Here, such an IPU may configured to perform traditional ISP relatedtasks in software and therefore no traditional ISP is actually residentin the platform (i.e., all stats and image signal processing functionsare performed in software by an IPU). In still other approaches, theISP/IPU sub-system may be implemented as a combination of dedicatedhardware statistics circuits, software executed on an IPU, and/or ISPhardware circuitry. Regardless, in implementations where IPU hardware1904 at least partially executes statistics software (or where ISP/IPUhardware 1904 acts as a co-processor or accelerator that receives morecoarse grained statistics related commands from a hardware statisticsengine 1905 rather than execute fine grained program code), the ISP/IPU1904 may contain a two-dimensional shift register array structure andperform reductions and/or generate histograms consistently with any ofthe discussions and teachings provided at length above. In suchembodiments, the ISP/IPU 1904 may be designed to include any/all of theIPU features described at length above in preceding sections.

Various hardware circuitry components of the ISP/IPU sub-system, may beintegrated on a large system-on-chip that also includes the processor1902 and other electrical functions (e.g., a graphics processing unit(GPU)). Although in many embodiments the processor 1902 may be aprocessing core of a computing system (such as a handheld device). Inother embodiments, the processor 1902 may be more tightly coupled to, oreven be a component of, the camera 1901.

The camera statistics engine 1905 calculates statistics from the pixeldata generated by the camera 1901. The statistics that are generated bythe statistics engine 1905 may then be employed for higher orderprocesses. For example, the statistics are forwarded to the processor1902 which performs higher level camera control functions using thestatistics, such higher level functions including auto-focusing,auto-exposing, and/or auto white balancing. The camera control functionmay be implemented, e.g., as software 1903 that executes on theprocessor 1902 (such as 3A camera control software associated with anAndroid operating system). Other types of statistics data for uses otherthan camera control may also be forwarded to the processor 1902 orelsewhere for other processes (e.g., statistics information for computervision software or hardware).

FIG. 20 shows a methodology described by the preceding discussions. Asobserved in FIG. 20, the method includes loading an array of contentinto a two-dimensional shift register 2001, where, the two-dimensionalshift register is coupled to an execution lane array. The method furtherincludes repeatedly performing a first sequence 2002 that comprises:shifting with the shift register first content residing along aparticular row or column into another parallel row or column wheresecond content resides, and performing mathematical operations with aparticular corresponding row or column of the execution lane array onthe first and second content. The method further includes repeatedlyperforming a second sequence 2003 that comprises shifting with the shiftregister content from a set of first locations along a resultant row orcolumn that is parallel with the rows or columns of the first sequenceinto a corresponding set of second locations along the resultant row orcolumn. The resultant row or column have values determined at least inpart from the mathematical operations of the first sequence. The secondsequence further includes performing mathematical operations on items ofcontent from the set of first locations and respective items of contentfrom the set of second locations with the execution lane array.

d. Implementation Embodiments

It is pertinent to point out that the various image processorarchitecture features described above are not necessarily limited toimage processing in the traditional sense and therefore may be appliedto other applications that may (or may not) cause the image processor tobe re-characterized. For example, if any of the various image processorarchitecture features described above were to be used in the creationand/or generation and/or rendering of animation as opposed to theprocessing of actual camera images, the image processor may becharacterized as a graphics processing unit. Additionally, the imageprocessor architectural features described above may be applied to othertechnical applications such as video processing, vision processing,image recognition and/or machine learning. Applied in this manner, theimage processor may be integrated with (e.g., as a co-processor to) amore general purpose processor (e.g., that is or is part of a CPU ofcomputing system), or, may be a stand alone processor within a computingsystem.

The hardware design embodiments discussed above may be embodied within asemiconductor chip and/or as a description of a circuit design foreventual targeting toward a semiconductor manufacturing process. In thecase of the later, such circuit descriptions may take of the form of a(e.g., VHDL or Verilog) register transfer level (RTL) circuitdescription, a gate level circuit description, a transistor levelcircuit description or mask description or various combinations thereof.Circuit descriptions are typically embodied on a computer readablestorage medium (such as a CD-ROM or other type of storage technology).

From the preceding sections is pertinent to recognize that an imageprocessor as described above may be embodied in hardware on a computersystem (e.g., as part of a handheld device's System on Chip (SOC) thatprocesses data from the handheld device's camera). In cases where theimage processor is embodied as a hardware circuit, note that the imagedata that is processed by the image processor may be received directlyfrom a camera. Here, the image processor may be part of a discretecamera, or, part of a computing system having an integrated camera. Inthe case of the later the image data may be received directly from thecamera or from the computing system's system memory (e.g., the camerasends its image data to system memory rather than the image processor).Note also that many of the features described in the preceding sectionsmay be applicable to a graphics processor unit (which rendersanimation).

FIG. 21 provides an exemplary depiction of a computing system. Many ofthe components of the computing system described below are applicable toa computing system having an integrated camera and associated imageprocessor (e.g., a handheld device such as a smartphone or tabletcomputer). Those of ordinary skill will be able to easily delineatebetween the two.

As observed in FIG. 21, the basic computing system may include a centralprocessing unit 2101 (which may include, e.g., a plurality of generalpurpose processing cores 2115_1 through 2015_N and a main memorycontroller 2117 disposed on a multi-core processor or applicationsprocessor), system memory 2102, a display 2103 (e.g., touchscreen,flat-panel), a local wired point-to-point link (e.g., USB) interface2104, various network I/O functions 2105 (such as an Ethernet interfaceand/or cellular modem subsystem), a wireless local area network (e.g.,WiFi) interface 2106, a wireless point-to-point link (e.g., Bluetooth)interface 2107 and a Global Positioning System interface 2108, varioussensors 2109_1 through 2109_N, one or more cameras 2110, a battery 2111,a power management control unit 2112, a speaker and microphone 2113 andan audio coder/decoder 2114.

An applications processor or multi-core processor 2150 may include oneor more general purpose processing cores 2115 within its CPU 2101, oneor more graphical processing units 2116, a memory management function2117 (e.g., a memory controller), an I/O control function 2118 and animage processing unit 2119. The general purpose processing cores 2115typically execute the operating system and application software of thecomputing system. The graphics processing units 2116 typically executegraphics intensive functions to, e.g., generate graphics informationthat is presented on the display 2103. The memory control function 2117interfaces with the system memory 2102 to write/read data to/from systemmemory 2102. The power management control unit 2112 generally controlsthe power consumption of the system 2100.

The image processing unit 2119 may be implemented according to any ofthe image processing unit embodiments described at length above in thepreceding sections. Alternatively or in combination, the IPU 2119 may becoupled to either or both of the GPU 2116 and CPU 2101 as a co-processorthereof. Additionally, in various embodiments, the GPU 2116 may beimplemented with any of the image processor features described at lengthabove.

Each of the touchscreen display 2103, the communication interfaces2104-2107, the GPS interface 2108, the sensors 2109, the camera 2110,and the speaker/microphone codec 2113, 2114 all can be viewed as variousforms of I/O (input and/or output) relative to the overall computingsystem including, where appropriate, an integrated peripheral device aswell (e.g., the one or more cameras 2110). Depending on implementation,various ones of these I/O components may be integrated on theapplications processor/multi-core processor 2150 or may be located offthe die or outside the package of the applications processor/multi-coreprocessor 2150.

In an embodiment one or more cameras 2110 includes a depth cameracapable of measuring depth between the camera and an object in its fieldof view. Application software, operating system software, device driversoftware and/or firmware executing on a general purpose CPU core (orother functional block having an instruction execution pipeline toexecute program code) of an applications processor or other processormay perform any of the functions described above.

Embodiments of the invention may include various processes as set forthabove. The processes may be embodied in machine-executable instructions.The instructions can be used to cause a general-purpose orspecial-purpose processor to perform certain processes. Alternatively,these processes may be performed by specific hardware components thatcontain hardwired logic for performing the processes, or by anycombination of programmed computer components and custom hardwarecomponents.

Elements of the present invention may also be provided as amachine-readable medium for storing the machine-executable instructions.The machine-readable medium may include, but is not limited to, floppydiskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASHmemory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards,propagation media or other type of media/machine-readable mediumsuitable for storing electronic instructions. For example, elements maybe downloaded as a computer program transferred from a remote computer(e.g., a server) to a requesting computer (e.g., a client) by way ofdata signals embodied in a carrier wave or other propagation medium viaa communication link (e.g., a modem or network connection).

In the foregoing specification, specific example embodiments have beendescribed. It will, however, be evident that various modifications andchanges may be made thereto without departing from the broader spiritand scope of the invention as set forth in the appended claims. Thespecification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

1. A method, comprising: loading an array of content into atwo-dimensional shift register, the two-dimensional shift registercoupled to an execution lane array; repeatedly performing a firstsequence comprising: shifting with the shift register first contentresiding along a particular row or column into another parallel row orcolumn where second content resides and performing mathematicaloperations with a particular corresponding row or column of theexecution lane array on the first and second content; and, repeatedlyperforming a second sequence comprising: shifting with the shiftregister content from a set of first locations along a resultant row orcolumn that is parallel with the rows or columns of the first sequenceinto a corresponding set of second locations along the resultant row orcolumn, the resultant row or column having values determined at least inpart from the mathematical operations of the first sequence, andperforming mathematical operations on items of content from the set offirst locations and respective items of content from the set of secondlocations with the execution lane array.
 2. The method of claim 1wherein the mathematical operations comprise addition.
 3. The method ofclaim 2 wherein the content comprises image intensity values.
 4. Themethod of claim 2 wherein the content comprises per bin counts of ahistogram.
 5. The method of claim 4 wherein content containing countsfor a set of bins of the histogram are shifted into a location havingcontent containing counts for the same set of bins of the histogram. 6.The method of claim 1 wherein the content is image content.
 7. Themethod of claim 1 wherein the second sequence further comprises:shifting with the shift register content from a second set of firstlocations along a second resultant row or column that is parallel withthe rows or columns of the first sequence into a corresponding secondset of second locations along the second resultant row or column, thesecond resultant row or column having values determined at least in partfrom the mathematical operations of the first sequence, and performingsecond mathematical operations on items of content from the second setof first locations and respective items of content from the second setof second locations.
 8. The method of claim 6 wherein the contentcomprises per bin counts of a histogram wherein the set of firstlocations and the second set of first locations include per bin countsof different bins of the histogram.
 9. The method of claim 8 furthercomprising, prior to the first and second sequences, merging storagespace nominally reserved for individual execution lanes and havinggroups of execution lanes write to merged storage space to update bincounts.
 10. The method of claim 1 further comprising repeatedlyperforming the loading, the first sequence and the second sequence overany of: an entire image globally; tiles of an image; a window of animage.
 11. The method of claim 10 wherein tile of an image are operatedover and further performing a context switch of accumulated contentacross processing of tile boundaries.
 12. A machine readable storagemedium containing program code that when processed by a processorcomprising a two-dimensional shift register coupled to an execution lanearray causes a method to be performed, comprising: loading an array ofcontent into the two-dimensional shift register; repeatedly performing afirst sequence comprising: shifting with the shift register firstcontent residing along a particular row or column into another parallelrow or column where second content resides and performing mathematicaloperations with a particular corresponding row or column of theexecution lane array on the first and second content; and, repeatedlyperforming a second sequence comprising: shifting with the shiftregister content from a set of first locations along a resultant row orcolumn that is parallel with the rows or columns of the first sequenceinto a corresponding set of second locations along the resultant row orcolumn, the resultant row or column having values determined at least inpart from the mathematical operations of the first sequence, andperforming mathematical operations on items of content from the set offirst locations and respective items of content from the set of secondlocations with the execution lane array.
 13. The machine readablestorage medium of claim 12 wherein the mathematical operations compriseaddition.
 14. The machine readable storage medium of claim 13 whereinthe content comprises image intensity values.
 15. The machine readablestorage medium of claim 13 wherein the content comprises per bin countsof a histogram.
 16. The machine readable storage medium of claim 15wherein content containing counts for a set of bins of the histogram areshifted into a location having content containing counts for the sameset of bins of the histogram.
 17. The machine readable storage medium ofclaim 12 wherein the content is image content.
 18. The machine readablestorage medium of claim 12 wherein the second sequence furthercomprises: shifting with the shift register content from a second set offirst locations along a second resultant row or column that is parallelwith the rows or columns of the first sequence into a correspondingsecond set of second locations along the second resultant row or column,the second resultant row or column having values determined at least inpart from the mathematical operations of the first sequence, andperforming second mathematical operations on items of content from thesecond set of first locations and respective items of content from thesecond set of second locations.
 19. The machine readable storage mediumof claim 17 wherein the content comprises per bin counts of a histogramwherein the set of first locations and the second set of first locationsinclude per bin counts of different bins of the histogram.
 20. Themachine readable storage medium of claim 19 further comprising, prior tothe first and second sequences, merging storage space nominally reservedfor individual execution lanes and having groups of execution laneswrite to merged storage space to update bin counts.
 21. The machinereadable storage medium of claim 12 further comprising repeatedlyperforming the loading, the first sequence and the second sequence overany of: an entire image globally; tiles of an image; a window of animage.
 22. The machine readable storage medium of claim 21 wherein tileof an image are operated over and further performing a context switch ofaccumulated content across processing of tile boundaries.
 23. Acomputing system, comprising: a plurality of processing cores; a memorycontroller coupled to a system memory, the memory controller coupled tothe plurality of processing cores; an image processor, the imageprocessor having a two-dimensional shift register coupled to anexecution lane array; a storage medium containing program code that whenprocessed by the image processor causes a method to be performed,comprising: loading an array of content into the two-dimensional shiftregister; repeatedly performing a first sequence comprising: shiftingwith the shift register first content residing along a particular row orcolumn into another parallel row or column where second content residesand performing mathematical operations with a particular correspondingrow or column of the execution lane array on the first and secondcontent; and, repeatedly performing a second sequence comprising:shifting with the shift register content from a set of first locationsalong a resultant row or column that is parallel with the rows orcolumns of the first sequence into a corresponding set of secondlocations along the resultant row or column, the resultant row or columnhaving values determined at least in part from the mathematicaloperations of the first sequence, and performing mathematical operationson items of content from the set of first locations and respective itemsof content from the set of second locations with the execution lanearray.
 24. The computing system of claim 23 wherein the mathematicaloperations comprise addition.
 25. The computing system of claim 24wherein the content comprises image intensity values.
 26. The computingsystem of claim 23 wherein the content comprises per bin counts of ahistogram.
 27. The computing system of claim 26 wherein contentcontaining counts for a set of bins of the histogram are shifted into alocation having content containing counts for the same set of bins ofthe histogram.